Study the architecture & organisation of modern processors, and influences upon these, with emphasis on pipelined RISC machines; gain understanding of the design of the memory subsystem, I/O, and system level interconnect; become proficient in the use of tools such as VHDL and SimpleScalar for the description, simulation, and verification of architectural designs; complete a series of assignments leading to the design, implementation, validation and assessment of a RISC system. It is assumed students are familiar with combinational and sequential logic design principles and have some experience in the use of CAD tools to describe and simulate digital systems.
Please note that the University reserves the right to vary student fees in line with relevant legislation. This fee information is provided as a guide and more specific information about fees, including fee policy, can be found on the fee website.
For advice about fees for courses with a fee displayed as "Not Applicable", including some Work Experience and UNSW Canberra at ADFA courses, please contact the relevant Faculty.
Where a Commonwealth Supported Students fee is displayed, it does not guarantee such places are available.