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Study the architecture & organisation of modern processors, and influences upon these, with emphasis on pipelined RISC machines; gain understanding of the design of the memory subsystem, I/O, and system level interconnect; become proficient in the use of tools such as VHDL and SimpleScalar for the description, simulation, and verification of architectural designs; complete a series of assignments leading to the design, implementation, validatation and assessment of a RISC system. It is assumed students are familiar with combinational and sequential logic design principles and have some experience in the use of CAD tools to describe and simulate digital systems.

Study Level


Offering Terms

Term 1



Delivery Mode

Fully on-site

Indicative contact hours


Conditions for Enrolment

Course Outline

To access course outline, please visit:


Pre-2019 Handbook Editions

Access past handbook editions (2018 and prior)

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